Test and debug pins are currently pinned out on Integrated Circuit (IC) packages such as Central Processing Unit (CPU) packages in the same available pin locations as the system functional signals. These test and debug pins must therefore be accounted for in the overall pin count budget imposed by a given pin count of a socket. This overall pin count budget is constrained by the package size as well as the need for proper mechanical “seating planes” to carry the large Land Grid Array (LGA) socket actuation forces. Therefore, they often impact the package size and the cost of the IC package.